Course Code: ENG103
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Synopsis

Upon the completion of the Digital Electronics Design course, students will be able to perform analysis and design of digital circuits. The course teaches the principles of digital circuit components that are the basic building blocks, and also the application of appropriate mathematical methods for modeling components and circuits.
Level: 1
Credit Units: 5
Presentation Pattern: EVERY REGULAR SEMESTER

Topics

  • Introductory concepts, number systems and codes
  • Describing logic circuits, combinational logic circuits
  • Flip-flops and relative devices
  • Digital arithmetic: Operations and circuits
  • Counters and registers
  • MSI logic circuits
  • Memory Devices
  • Programmable logic device architectures

Learning Outcome

  • Give the conversion from one number system to another.
  • Execute arithmetic operation on binary numbers.
  • Use Boolean algebra theorems and Karnaugh maps to simplify logic circuits.
  • Recall the operation of flip-flops and basic logic circuits.
  • Sketch the timing diagram.
  • List the truth table for logic circuits.
  • Design synchronous / asynchronous digital circuits.
  • Implement logic expressions using logic gates/ multiplexer/ encoder/ decoder.
Part-time Programmes / CET Courses

Who Should Attend

Executive who requires knowledge on Digital Electronics Design.


Relevance of Course to employment/upskilling/reskilling

This course provides introduction to analysis and design of simple digital circuits. It equips learners with foundational knowledge required to pursue advanced circuit design essential for an electronic circuit design engineer.


Admissions Prerequisites

  • Diploma or an equivalent qualification from a recognized institution.

Please refer to Undergraduate CET Admission Eligibility Criteria for Undergraduate CET Modular Courses.

 

Schedule

WeekDayTimeTopic
2Thursday7pm - 10pmIntroductory concepts, number systems and codes
4Thursday7pm - 10pmDescribing logic circuits, combinational logic circuits
6Thursday7pm - 10pmFlip-flops and relative devices
8Thursday7pm - 10pmDigital arithmetic operations and circuits, Counters and registers
10Thursday7pm - 10pmMSI logic circuits
12Thursday7pm - 10pmMemory devices, Programmable logic device architectures

 

Assessments

The overall course grade is determined by

  • Assignments, Practical Exam, Written Exam

 

Trainer Info

Dr Toh Eng Huat is currently with GlobalFoundries, where he works on logic and non volatile memory (NVM) technologies, as well as next generation memory solutions such as spin transfer torque magnetic random access memory (STT MRAM) and resistive random access memory (ReRAM). His technical expertise also extends to magnetic sensors and optical sensors.

With more than 15 years of experience in the semiconductor industry, Dr. Toh serves as a device lead/manager, where he drives and leads teams in delivering a diversified and advanced portfolio of semiconductor technologies from concept to production.

Dr. Toh received both his Doctor of Philosophy (PhD) and Bachelor of Engineering (BEng) degrees from the National University of Singapore (NUS). His research interests cover a broad range of areas, including novel semiconductor devices, next generation memory technologies, magnetic sensing, and optical sensing.

He is a prolific contributor to the field, having authored or co authored more than 70 journal and conference publications and he holds over 190 U.S. patents in the semiconductor domain.


Dr Paul Loh Ruen Chze is a Senior Lecturer in the School of Science and Technology at the Singapore University of Social Sciences (SUSS). He holds a PhD in Computing and has extensive experience across academia and industry, including roles at Hewlett‑Packard, Compaq, and Digital Equipment Corporation. His teaching and research interests focus on Internet of Things (IoT), wireless communications, and IoT security, with publications in leading IEEE journals and conferences. Dr Loh is committed to practice‑oriented education that bridges academic theory with real‑world applications.


Course Completion requirements

  • Participants are required to achieve at least 75% attendance and pass any prescribed examinations/assessments or submit any course/project work (if any) under the course requirement.
  • Participants are required to complete all surveys and feedbacks related to the course.
  • The course fees are reviewed annually and may be revised. The University reserves the right to adjust the course fees without prior notice.
  • Singapore University of Social Sciences reserves the right to amend and/or revise the above schedule without prior notice.

 

Course Fees, payment and refund policy

  International Participants Singapore Citizens (below 40yrs), Permanent Residents Singapore Citizens (40yrs and above) SkillsFuture Mid - Career Enhanced Subsidy1Enhanced Training Support for SMEs2 (Singaporean and PRs)
Full Course Fees (A) $2,323.00$1,936.00$1,936.00 $1,936.00
SSG Grant Rate (B) 0%70%70%70%
SSG Grant (C)- $1,355.20$1,355.20$1,355.20
Nett course fees
(A) - (C) = (D) 		$2,323.00$580.80$580.80$580.80
9% GST on Nett course fees (E)$209.07$52.27$52.27$52.27
SSG Enhanced Funding Rate (F)0%0%20%20%
SSG Enhanced Grant (G)-- $387.20$387.20
Total nett course fee payable, including GST
(D) + (E) - (G) = (H)		$2,532.07$633.07$245.87$245.87

1 Mid-Career Enhanced Subsidy: Singaporeans aged 40 and above may enjoy subsidies up to 90% of the course fees.
2 Enhanced Training Support for SMEs: SME-sponsored employees (Singapore citizens and PRs) aged 21 and above may enjoy subsidies up to 90% of the course fees.

For the various payment modes, please refer here.

For the refund policy, please refer here. 

For clarification, please contact the SUSS Academy via the following:

Telephone: +65 6248 0263
Email: [email protected]