Course Code: ENG105
Synopsis
The central theme of this course is the analysis, specification and design of a wide variety of digital circuits. Students will learn the theory and application of logic design methods, and use computer-based design packages widely employed in industry. They will undertake design exercises, translating system specifications into circuits that could then be simulated on the computer.
Level: 1
Credit Units: 5
Presentation Pattern: EVERY REGULAR SEMESTER
Topics
- Introduction to VHDL
- VHDL for combinational logic devices
- VHDL for sequential logic devices
- Logic Function Optimization
- Synchronous sequential circuit design
- Synchronous sequential circuit analysis
- Asynchronous sequential circuit analysis
- Asynchronous sequential circuit design
- State reduction and assignment in asynchronous sequential circuiy design
- Hazards in asynchronous sequential circuit
- Testing of digital logic circuits
Learning Outcome
- Draw gate-level schematic diagrams and signal waveforms for logic circuits.
- Use Boolean Algebra, Karnaugh map, Quine-Mc-Cluskey methods to simplify logic circuits for optimal costs.
- Identify the prime implicants, static hazards and other characteristics of logic circuits.
- Present the state diagram, excitation table, state table and flow table for FSM.
- Implement logic circuits and logic functions using suitable components.
- Give cost, minimized expression, test vectors for logic circuits.
- Write VHDL code for corresponding logic circuits and logic functions.
- Design logic systems for the specified requirements.
Who Should Attend
Executive who requires knowledge on Design of Logic Systems.
Relevance of Course to employment/upskilling/reskilling
This course provides introduction to analysis and design of simple logic systems. It equips learners with foundational knowledge required to pursue advanced circuit design essential for an electronic circuit design engineer.
Admissions Prerequisites
- Diploma or an equivalent qualification from a recognized institution.
Please refer to Undergraduate CET Admission Eligibility Criteria for Undergraduate CET Modular Courses.
Schedule
| Week | Day | Time | Topic |
|---|---|---|---|
| 1 | Tuesday | 7pm - 10pm | Introduction to VHDL |
| 3 | Tuesday | 7pm - 10pm | VHDL for combinational logic devices, VHDL for sequential logic devices |
| 5 | Tuesday | 7pm - 10pm | Logic Function Optimization, Synchronous sequential circuit design |
| 7 | Tuesday | 7pm - 10pm | Synchronous sequential circuit analysis, Asynchronous sequential circuit analysis |
| 9 | Tuesday | 7pm - 10pm | Asynchronous sequential circuit design, State reduction and assignment in asynchronous sequential circuit design |
| 11 | Tuesday | 7pm - 10pm | Hazards in asynchronous sequential circuit, Testing of digital logic circuits |
Assessments
The overall course grade is determined by
- Practical Exam, Written Exam, Assignments
Trainer Info
Dr. Pham The Hanh received the Bachelor of Engineering (B.Eng.) degree in Electronics and Telecommunications Engineering, graduating with First Class Honors, from the Hanoi University of Technology, Vietnam, in 2001. He subsequently earned the Doctor of Philosophy (Ph.D.) degree from the National University of Singapore (NUS) in 2008.
Dr. Pham is currently a Lecturer at the School of Engineering (SoE), Ngee Ann Polytechnic. Prior to his academic appointments, Dr. Pham worked as a Scientist at the Institute for Infocomm Research (I²R), A*STAR. Earlier, from September 2007 to February 2011, he held the position of Research Engineer/Research Fellow in the Department of Electrical and Computer Engineering at the National University of Singapore.
His research interests span machine learning algorithms for bioengineering, wireless communications, and communication theory, with particular emphasis on relay networks, cognitive radio, orthogonal frequency division multiplexing (OFDM), and multiple input multiple output (MIMO) systems.
Course Completion requirements
- Participants are required to achieve at least 75% attendance and pass any prescribed examinations/assessments or submit any course/project work (if any) under the course requirement.
- Participants are required to complete all surveys and feedbacks related to the course.
- The course fees are reviewed annually and may be revised. The University reserves the right to adjust the course fees without prior notice.
- Singapore University of Social Sciences reserves the right to amend and/or revise the above schedule without prior notice.
Course Fees, payment and refund policy
| International Participants | Singapore Citizens (below 40yrs), Permanent Residents | Singapore Citizens (40yrs and above) SkillsFuture Mid - Career Enhanced Subsidy1 | Enhanced Training Support for SMEs2 (Singaporean and PRs) | |
|---|---|---|---|---|
| Full Course Fees (A) | $2,323.00 | $1,936.00 | $1,936.00 | $1,936.00 |
| SSG Grant Rate (B) | 0% | 70% | 70% | 70% |
| SSG Grant (C) | - | $1,355.20 | $1,355.20 | $1,355.20 |
| Nett course fees (A) - (C) = (D) | $2,323.00 | $580.80 | $580.80 | $580.80 |
| 9% GST on Nett course fees (E) | $209.07 | $52.27 | $52.27 | $52.27 |
| SSG Enhanced Funding Rate (F) | 0% | 0% | 20% | 20% |
| SSG Enhanced Grant (G) | - | - | $387.20 | $387.20 |
| Total nett course fee payable, including GST (D) + (E) - (G) = (H) | $2,532.07 | $633.07 | $245.87 | $245.87 |
1 Mid-Career Enhanced Subsidy: Singaporeans aged 40 and above may enjoy subsidies up to 90% of the course fees.
2 Enhanced Training Support for SMEs: SME-sponsored employees (Singapore citizens and PRs) aged 21 and above may enjoy subsidies up to 90% of the course fees.
For the various payment modes, please refer here.
For the refund policy, please refer here.
For clarification, please contact the SUSS Academy via the following:
Telephone: +65 6248 0263
Email: [email protected]